In a high speed synchronous semiconductor memory device such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a data unit is transferred (input from or output to) to other devices in synchronization with an external clock signal. That is, the high speed synchronous semiconductor memory device such as the DDR SDRAM performs an input or output operation in synchronization with not only a rising edge but also a falling edge of the external system clock signal. Typically, in a system or a circuit including a semiconductor memory, a clock signal is used as a reference signal for adjusting or controlling an operation timing or guaranteeing a high-speed operation without any error. Accordingly, for a high speed operation of the semiconductor memory device, it is required that operations thereof are synchronized with the external clock signal.
When an internal clock signal input is derived from an external clock signal is used in internal circuits, the internal clock signal is delayed and a clock skew is generated because of the internal circuits. For compensating the clock skew in order to equalize a phase of the internal clock signal with that of an external clock signal, a synchronization control circuit such as a delay locked loop (DLL) is embedded in the system or the circuit. The DLL receives an external clock signal and controls a timing of outputting data from the semiconductor memory device to thereby synchronize the timing with the external clock signal.
FIG. 1 is a block diagram of a conventional delay locked loop (DLL).
As shown, the conventional delay locked loop (DLL) includes a clock buffer 10, a delay block 30, a phase comparator 50, a delay controller 40, a delay replica model 60, a duty cycle compensator 70, and a driver 80.
The clock buffer 110 receives an external clock signal CLK and an external clock bar signal /CLK to generate internal clocks.
The delay block 30 is for delaying the internal clocks, wherein a delay amount of the delay block 30 is determined by the phase comparator 50 and the delay controller 40 determines a delay path included in the delay block 30 based on the delay amount. The delay block 30 includes at least one delay line constituted with plural unit delay cells, each including either logic NAND gates or a logic NAND gate and an inverter.
The delay controller 40 includes a logic circuit for determining a delay amount in the delay path of the delay block 30 and a bidirectional shift register for determining a direction of the delay amount.
The phase comparator 50 compares a phase of a reference clock signal REF_CLK, one of the internal clocks output from the clock buffer 10, with that of a feedback clock FBR_CLK output from the delay replica model 60 to thereby control the delay controller 40 based on the comparison result.
The delay replica model 60 delays an output of the delay block 30 by a predetermined amount estimated from a clock path and data path where data or the clock signal passes on in the semiconductor memory device. That is, the delay replica model 50 includes replica delay elements located in clock signal paths: one is from an input pin, i.e., inside of the chip, to the delay block 30, and the other is from the delay block 30 to an output pin.
The duty cycle compensator 70 is for controlling a duty ratio of clock output from the delay block 30 to thereby set 50:50 of the duty ratio.
The driver 80 receives outputs, i.e., IFBR_CLK and IFBR_CLK, of the duty cycle compensator 70 and outputs plural DLL clocks to external circuits.
FIG. 3 is a block diagram describing the driver 80 shown in FIG. 1.
As shown, the driver 80 includes a phase splitter 82, a first driving block 84, and a second driving block 86.
The first driving block 84 includes a first DLL driver 84_1 and a second DLL driver 84_2 for generating a first rising DLL clock RCLK_DLL and a first falling DLL clock FCLK_DLL. Likewise, the second driving block 86 includes a third DLL driver 86_1 and a fourth DLL driver 86_2 for generating a second rising DLL clock RCLK_DLLOE and a second falling DLL clock FCLK_DLLOE. Herein, the first driving block 84 and the second driving block 86 receives the same clock signals from the phase splitter 82, and detailed composition of the first driving block 84 is similar to that in the second driving block 86.
FIG. 4 is a schematic circuit diagram of a DLL driver, e.g., the first to fourth DLL drivers shown in FIG. 3.
The first to fourth DLL drivers 84_1, 84_2, 86_1 and 86_2 have the same elements. Referring to FIG. 4, each DLL driver includes one logic NAND gate ND and an even number of inverters, e.g., two inverters INV1 and INV2. The logic NAND gate ND receives a clock input CLKB_IN and an enable signal EN. The clock input CLKB_IN can correspond to outputs RCLK_OUT and RCLKB_OUT of the phase splitter 82 shown in FIG. 3, and the enable signal EN can be matched with driver enable signals DRV_EN and DRVOE_EN shown in FIG. 3.
FIG. 5 is a schematic circuit diagram of the phase splitter 82 shown in FIG. 3.
As shown, the phase splitter 82 includes a first circuit for generating a rising-out clock signal RCLK_OUT and a second circuit for generating a rising-out bar signal RCLKB_OUT. The first circuit includes two inverters INV82_1 and INV82_2 and two MOS option blocks MC82_1 and MC82_2, and the second circuit includes three inverters INV82_3, INV82_4 and INV82_5 and two MOS option blocks MC82_3 and MC82_4. Both the first and second circuits receive a rising delayed clock IFBR_CLK, one of delayed clocks IFBR_CLK and IFBF_CLK, through an input terminal RCLK_IN of the phase splitter 82. An input loading block 82_8 is coupled to another input terminal FCLK_IN, for receiving a falling delayed clock IFBF_CLK, the other of delayed clocks IFBR_CLK and IFBF_CLK. Though the input loading block 82_8 floats, as shown in FIG. 5, the input loading block may be connected to the first and second circuits when the falling delayed clock IFBF_CLK input through the input terminal FCLK_IN is used.
Referring to FIGS. 3 to 5, the driver 80 generates the first rising and falling DLL clocks FCLK_DLL and RCLK_DLL and the second rising and falling DLL clocks FCLK_DLLOE and RCLK_DLLOE, wherein the first rising and falling DLL clocks FCLK_DLL and RCLK_DLL and the second rising and falling DLL clocks FCLK_DLLOE and RCLK_DLLOE have the same delay amount. Because the first to fourth DLL drivers have the same elements, rising edges of the first rising DLL clock RCLK_DLL and the second rising DLL clock RCLK_DLLOE occur at the same time; likewise, falling edges of the first falling DLL clock FCLK_DLL and the second falling DLL clock FCLK_DLLOE occur at the same time.
A DLL is generally used during only read operation of a semiconductor memory device. However, in the conventional DLL shown in FIG. 1, the first rising and falling DLL clocks FCLK_DLL and RCLK_DLL are used during the read operation for outputting data in response to a read command, and the second rising and falling DLL clocks FCLK_DLLOE and RCLK_DLLOE are used during a write operation for generating plural read control signals controlling blocks or circuits in a read path of data during the write operation to thereby reduce current consumption during the write operation.
FIG. 6 is a schematic circuit diagram of a data output clock generator in a conventional semiconductor memory device.
As shown, the data output clock generator receives outputs of the conventional DLL shown in FIG. 1 and generates data output clock signals RCLK_D0 and FCLK_D0 in response to data output enable signals ROUTEN and FOUTEN. The data output clock signals RCLK_D0 and FCLK_D0 are used for outputting data from a data output buffer to external devices in synchronization with an external clock signal.
FIG. 2 is a timing diagram demonstrating operation of the conventional delay locked loop shown in FIG. 1. Hereinafter, detailed operation of the conventional DLL is described.
As above described, the first rising and falling DLL clocks FCLK_DLL and RCLK_DLL are used for outputting data in response to a read command, and the second rising and falling DLL clocks FCLK_DLLOE and RCLK_DLLOE are used for generating plural read control signals during a write operation.
The second rising and falling DLL clocks FCLK_DLLOE and RCLK_DLLOE are also used in a read enable block for generating rising/falling data output enable signal ROUTEN and FOUTEN. The rising/falling data output enable signals ROUTEN and FOUTEN are for drawing the data output clock signals RCLK_D0 and FCLK_D0 from the first rising and falling DLL clocks FCLK_DLL and RCLK_DLL, as shown in FIG. 6, in order to output data according to a column address strobe (CAS) latency and bust length (BL) at read operation. Output blocks using the first rising and falling DLL clocks FCLK_DLL and RCLK_DLL, and the second rising and falling DLL clocks FCLK_DLLOE and RCLK_DLLOE will be described in detail with the following drawings.
Referring to FIG. 2, the conventional DLL performs a locking operation to achieve a locking state such that rising/falling edges of the reference clock REF_CLK coincide with those of the feedback clock IFBR_CLK before a read operation of the semiconductor memory device.
The rising data output enable signal ROUTEN is generated by a rising edge of the second falling DLL clock FCLK_DLLOE; herein, there is a phase difference between the rising data output enable signal ROUTEN and the second falling DLL clock FCLK_DLLOE because of a delay. The delay should be shorter than 0.5*tCK (wherein tCK corresponds to one clock cycle). Since the data output clock signals RCLK_D0 and FCLK_D0 are generated by results of logic AND operations to each of the rising/falling data output enable signals ROUTEN and FOUTEN and each of the first rising/falling DLL clocks FCLK_DLL and RCLK_DLL respectively, malfunctions can be caused if the delay is longer than 0.5*tCK. Referring to FIG. 6, if the delay, i.e., a time gap between rising edges of the rising data output enable signal ROUTEN and the second falling DLL clock FCLK_DLLOE, is longer than 0.5*tCK, the rising data output enable signal ROUTEN is generated after a rising edge of the first rising DLL clock RCLK_DLL. In this case, after performing the logic AND operation, the data output clock signals RCLK_D0 and FCLK_D0 are not generated in a desirable time; accordingly, malfunctions occur in the semiconductor memory device.
As the operation frequency of the semiconductor memory device becomes higher, a permissible range of the delay is narrower than 0.5*tCK. For example, if an operation frequency is 1 Gbps, i.e., 1 tCK=2 ns, the rising data output enable signal ROUTEN are generated within 1.0 ns (=0.5*2 ns). If an operation frequency is 1.6 Gbps, i.e., 1 tCK=1.25 ns, the rising data output enable signal ROUTEN is generated within 625 ps.
Accordingly, as operation frequency becomes higher in the semiconductor memory device including the conventional DLL, an operation margin for generating the rising/falling data output enable signal ROUTEN and FOUTEN becomes less. Thus, the operation frequency of the semiconductor memory device is limited.